Recently, semiconductor devices become more highly integrated. When a plurality of highly integrated semiconductor devices are arranged within a horizontal plane and connected with one another by wiring into a product, the wiring length may increase to lead to an increase in resistance of the wiring and increase in a wiring delay.
Hence, it is proposed to use the three-dimensional integration technology of integrating the semiconductor devices in three dimensions. In this three-dimensional integration technology, for example, a bonding apparatus is used to bond two semiconductor wafers (hereinafter, referred to as “wafers”). The bonding apparatus has, for example, a fixed table mounting a wafer on its upper surface and a movable table disposed opposite to the fixed table and capable of rising and lowering while suction-holding the wafer on its lower surface. In each of the fixed table and the movable table, a heater is embedded. The bonding apparatus superposes the two wafers and then presses them by applying a load by using the fixed table and movable table while heating the wafers by using the heaters, whereby the two wafers are bonded together (Patent Document 1).    [Patent Document 1] Japanese Laid-open Patent Publication No. 2004-207436